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Altera_Forum's avatar
Altera_Forum
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15 years ago

NIOS + IRQ + custom component

Hi, I'm trying to interrupt a Nios Prosessor whit a Custom Component and setup a successful interrupt routine. But I can't Do it. The problem is that i can't find a complete example of a custo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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There are some systems [1] where it is possible to exit the ISR before the write

(2) has propogated far enough to actually cause the IRQ line to be deasserted. This can cause 'splurious' ISR messages under certain loads.

[1] eg when the write gets 'posted' on some bus, and the check (3) involves looking in shared memory (typical of ethernet receive).

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ah I just remember..:eek: maybe my case is same as like what dsl said. The program exits the ISR earlier before the 'write' signal comes. Now I'm modifying my components interface signal behavior. Let me see whether it will fix my problem or not..:confused:

Thanks