Honored Contributor
Honored ContributorI would make the IRQ signal indefinite - ie stay active until the ISR clears the source.
The IRQ can then be a logical 'or' of all the bits of the MM slave register. You then need to do 'write to clear' on that location from the nios. The ISR then does: 1) Read IRQ register 2) Write the value back to clear the IRQ bits that were present at the time it was read. 3) Check each IRQ bit in turn (or fifo level (etc)) to actually service the interrupt. 4) exit from ISR There are some systems [1] where it is possible to exit the ISR before the write (2) has propogated far enough to actually cause the IRQ line to be deasserted. This can cause 'splurious' ISR messages under certain loads. [1] eg when the write gets 'posted' on some bus, and the check (3) involves looking in shared memory (typical of ethernet receive).
