Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi Fightingdreamer,
Not sure if you are implementing the procedure correctly. Process I implemented was: 1. IRQ signal ( interrupt sender) is generated. This signal needs to have a period of typically 50 clocks wide (wrt Nios Clock). 2. The IRQ signal is used to simultaneously set an IRQ bit in an avalon MM register, i.e. Status reg within your custom component. Process 1 alerts the NIOS to an interrupt event and points to the entry point of your ISR code. The ISR code reads and clears the IRQ bit (set in Process 2) before exiting the ISR. Hope this helps, Ken.