NIOS + IRQ + custom component

Hi Fightingdreamer,

The IRQ signal needs to be >> 1 clock period wide. The CPU invokes initial processing to ID the interrupt and select the correct handler. Sorry I can post links but google NIOS II Exception Handling by John Loomis and look at alterawiki for IRQ code. In my case I had to make the IRQ pulse 50 clock cyles wide. I presently don't know of any Altera guidelines on this (Is there one?).

I would suggest the interrupt sender should be assigned to the MM slave (a custom CSR interface ??) were you should clear the defined IRQ bit before existing the ISR.

Hope this is helpful.

kohagan.