Forum Discussion
Altera_Forum
Honored Contributor
16 years agoI cannot follow your description, the last paragraph with the defining of the top level is a bit confusing.
I think what you mean is how to define the clock as input signal. That you must do in your verilog file, where you define the pins. The direction then appears in the pinplanner after synthesis I think. (Can't follow your steps, as I am not sitting before Quartus right now.)