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Altera_Forum
Honored Contributor
16 years agoThe design uses a verilog file for the system design, in this they first defined the Input/Output Pins. (for LED here it is: output [ 1: 0] top_led; )This Pins are connected to wires. These are also named (for the LED wire here wire [ 1: 0] top_led; ) and this wire connects the OutputPin of the NIOS Core. The outputport from the NIOS is then connected to the busses or components in the NIOS, but that isn't in the verilog toplevelfile anymore. (here .out_port_from_the_led_pio (top_led), where out_port_from_the_led_pio is the portname of the NIOS Side and connects to top_led)
Your code should work (with 0x0F) I have tried it and it works as you expected it. I have attached the compressed project to this thread. The C-Code is in the zip as txt-File. Perhaps you look more into creating a NIOS System. I have generated a NIOS-Core very simple for this demo, to test. It has just a CPU, Memory and the PIO. The design I have created as a blockshematic. In my opinion for first start this is a bit better to read, also it work like the verilog file or vhdl. (the names of the project are messed up, because I stripped an old project for this, so just ignore the filenames) (some more tipps for start: read the manuals, they are quite good. Never add spaces to pathes when working with altera tools. when you update your nios core sometimes you have to regenerate your bsp to get the nios code working again. make backups of working code before further editing. Some path are absolute in the designs, so don't move project folders. while in the SOPC Builder, you can deactivate modules by clicking the green arrows on the left. Sometimes this saves a lot of time, because the parameters does not have to put in later again, you can just reactivate.) Good Luck with the NEEK. ;-)