New version of NiosII Flash Programmer

joe,

Ok ... now I'm up to speed after reading the other topic.

> I do not have a reset signal - only a watchdog reset input which I do

> not connect to the programmer design, since I don't want to reset it!!!

> So at the moment I just tie reset to vcc on the schematic?

This is probably your problem ... I have a similar situation as you on one

of my boards, so I dropped in a little delay counter that drives the system

module reset_n. Here's what I use with the programmer design:

module cpurst (
        clk,
        rsti_n,
        rsto_n
);
input        clk;
input        rsti_n;
output     rsto_n;
/* Counter width, delay is 1 << (cw-1) */
parameter cw  = 9;
reg        cnt;
always @(posedge clk)
        if (rsti_n == 0) cnt = 1&#39;b0;
        else if (cnt == 0) cnt = cnt + 1&#39;b1;
assign rsto_n = cnt;
endmodule

You can just tie rsti_n to Vcc, clk to your device clk input and rsto_n to

the system module reset_n.

Regards,

--Scott