Honored Contributor
Honored Contributor<div class='quotetop'>QUOTE (jan @ Sep 11 2009, 11:20 AM) <{post_snapback}> (index.php?act=findpost&pid=23815)</div>
--- Quote Start --- ... but experiences shows to HDL designers, that using proved components is allways much better option.[/b] --- Quote End --- I did not vote for not using the "proven HDL design". I just said that if it can be accessed by the CPU via the Avalon bus, it also can be accessed via a (new) dedicated Avalon-bus-mastering HDL (DMA-type) component. What I maybe would do, is not enhance the proven hdl component (e.g. by FIFOs), but create an additional HDL component that accesses it via the Avalon bus. The Avalon bus is clever enough to allow for multiple accesses from different masters to different slaves at the same time, so just by configuration done by software, you can have your the "DMA-Controller" use the normal Linux RAM (introducing bus conflict that the Avalon bus solves by delays) or a dedicated on-chip ram (no bus conflicts). IMHO this is easier to do, better testable and more flexible than a design with dedicated FIFOs. -Michael
