need help on dma

I have a custom logic wrote by myself. There's a DCFIFO in the logic. And when the fifo is full, NIOS II cpu will get an interrupt, then cpu will get(read) data out of the fifo. Every thing seems all right.

 
rdclk <= csi_clk; --rdclk is the read clock of the dcfifo
 
process(csi_reset, csi_clk)
begin
     if csi_reset = '1' then
         rdreq <= '0';
     else
         if falling_edge(csi_clk) then
              if avs_read = '1' and avs_address = "001" then
                  rdreq <= '1';  --rdreq is read request of dcfifo
              else
                  rdreq <= '0';
         end if;
     end if;
end process;
 
process(csi_reset, csi_clk)
begin
      if csi_reset= '1' then
          avs_readdata <= (others=>'0');
      else
          if rising_edge(csi_clk) then
              if (avs_read = '1' and avs_chipselect = '1') then
                  if avs_address = "001" then
                       avs_readdata <= q; --q is output of dcfifo
                  end if 
               end if;
          end if;
       end if;
end process;