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Altera_Forum
Honored Contributor
Honored ContributorNeed help fixing U-Boot for custom board- Nios2
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0 nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate) ................................................................................ ............... -UoBto1 1.3.( aM r422 00 6 -611::601 )PC U :iNsoI- IYSIS D :ffffffff ,Wed Dec 13 32:95:95 9196BOARD : Altera EP-1C20 *** Warning - bad CRC, using default environment ................................................................................ ............... Above is the output that i got over Jtag Uart. As u can see the initial message printed by the bootloader is in Little endian format. i.e. U-Boot 1.1.3 is printed as -UoBto1 1.3. All data that is read from memory and printed over Jtag are printed in Little endian format. I tried to debug using Insight. Data that is printed is using printf statement. This calls vsprintf. When data is passed to printf it appears alright but when is passed to vsprintf it changes as above. I also checked the code for vsprintf. It is correct. Can any 1 tell me what can be the problem.2 Replies
Altera_ForumHi shakthi,
I have never observed this problem, nor have I ever received notice that such a problem exists from any other Nios-II u-boot users. Have you solved this problem yet? And how did you generate your binary image? It looks like the type of problem that occurs when you use a custom tool that doesn't properly handle endian-order issues. Regardless, if it's a u-boot problem, I'd like to get it fixed -- please provide an update. Regards, --Scott- Altera_Forum
A follow up for anyone monitoring this thread:
This is a hardware problem, not a problem with u-boot. Please see: http://forum.niosforum.com/forum/index.php...indpost&p=13897 (http://forum.niosforum.com/forum/index.php?act=st&f=18&t=3609&hl=&view=findpost&p=13897) Regards, --Scott
