Honored ContributorI am looking to implement a NAND controller (Cyclone II C35) that interfaces directly with 2GB NAND devices (Samsung K9WAG08U1A).
User experiences and or sample verilog code would be very helpful. Thank you, Chris
Honored ContributorYou can connect the chip to a PIO and simulate the requested bus cycles in software. You probably already have drivers for the flash (Samsong seems to provide a Linux file system), so you only need to write the low level part (PIO generating bus cycles).
If you are a bit careful with the software implementation, you can later create a VHDL interface connected to Avalon MM in SOPC builder, and only modify the low level part of the driver. IzIHonored ContributorThen what will be the max frequency of the Pio? Well in fact if it is running by software will I be able to run it at low latency?
Honored Contributorddrdrive,
did you implement the solution by software?Honored Contributor
did you implement the solution by software?
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--- Quote End --- No, hardware only solution. Thanks, Chris
Honored ContributorAny update? Did you implement with PIO?
Did you do timing analysis? What is fmax? Are you bursting? Is this synchronous? Ted
