Multiple NIOS same memory code

I don't think there is anything that will stop that working, however it would require extreme care as all the data would have to be separate.

You might manage that with a fully custom 'OS' but the commerial OS won't run that way.

Clearly 'tightly coupled' instruction memory can only be shared between 2 cpu - and then only if initialised in the fpga image.

On-chip instruction memory accessed through the Avalon MM interface will probably give a performance penalty when the same block ends up being accessed by more than one cpu concurrently (compared to each using a separate block - but tightly coupled is much better anyway).

External (SDRAM/DDR) memory accesses won't be any worse than if the cpus are accessing different regions - indeed they may be better if the memory page doesn't need changing (CAS only access).