Honored ContributorHello,
I need a way for an Avalon peripheral to detect which master is accessing it in a multi-master environment. I have a design with a NIOS processor and the PCI Master-Target. I want some of the bits in one of the PCI BAR's to be read only for the PCI core, but be read/write for the NIOS. Can anyone think of a way to do this? I was thinking of using arbiterlock from the NIOS. Thank you, Jeff
Honored Contributorthrough a dual slave component in from of the component, make the one read only. the other rw. put a master to access the peripheral in question.
you will have to handle your own arbitration.Honored ContributorI'd rather skip my own arbiter if possible, but you gave me an idea.
What about 2 avalon slaves on the same avalon bus, each with a conduit to pass the control signals out to the same registers? The first master would only access the first slave device and the second master would only access the second slave device. That way I should be able to tell which device is accessing the registers and control the access, but still use the avalon arbiter. The second device is the PCI core, so I would prefer to take advantage of all of the built in arbitration and control of the avalon interface.Honored ContributorIf this is a custom peripheral then making it a dual port with the permissions differing between the two ports would be how I would approach this problem. You wouldn't need to use conduits since there is no limit to how many master, slave, clock, sink, and source ports a single component can have.
Honored ContributorGood point, but can you compile a peripheral with 2 ports? I know you can create one with 2 IRQ's, but you can't compile it.
Honored ContributorYes, if you are creating a custom component you can give it as many avalon slaves as you'd like. This is the method I would use for what you are trying to do.
JakeHonored ContributorAnother alternative would be to add an extra address bit to your avalon slave port. Have the one master address your slave with the upper bit set and the other with it cleared. Then you can simply use the address bit to determine whether or not to grant write access.
JakeHonored ContributorThank you!
Honored ContributorAbout the interrupt thing, you are limited to one interrupt sender/receiver per slave/master port. So if you create a component with two slave ports you can have one interrupt per port. You would want to make sure that those interrupts don't fire at the same time if a master is connected to both ports since you'll end up with two interrupts for a single event which would get a bit confusing to handle in software :)
Users who want to have multiple interrupts from the same slave port should have a register that can be read back to determine which event occurred as apposed to attempting to use multiple interrupt lines (which isn't supported anyway)
