multi Nios connect to One Pcie

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Thanks for your replies.

After your advices, I redesign my system and I'm going to implement it in a single Qsys design and each cpu as a subdesign.

Is there any thing that i should care if i use one share memory for more than one cpu? (read while write and rtc.)

Is there any need to use some things like hardware mutex?

All my writes and reads to share memory, are done with IORD_32DIRECT and IOWR_32DIRECT. And i thinks these are atomic operation. Am i wright?

Does Avalon interface control these operations or I should use DMA?

Thanks.

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Although it is designed without the multex in Quartus successfully,does it works well in "Hello world"programe in the Nios IDE ?Does it can work in ucOS or ucLinux?

Thank you for reply!

Kinder Regards!