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I could not get a clear on the IRQ pin by writing to CSR status, 1 or 0. Only resetting the unit cleared the IRQ line, it was clearly visible in SignalTap. Of course I am making a mistake somewhere but I found a suitable work around for now. I let the data valid lines of CVI determine the packet size. I have no issues with transfer length when the fifo buffer in CVI is greater than the amount of pixels in one line. I removed the EOP interrupt enable and just let the DMA controller run freely using one descriptor written in the vsync ISR but the mSGDMA unit must be reset first. No problem, time enough during vsync anyway. The transfer length is stable as expected.
I did find the TSE example but did not dig into that because it involved a Yocto patch and it seemed to be a set of binaries rather then useful source. Could be wrong about that because I did not look at the content of the ZIPs.
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Glad you worked something out-- I had to do the same. I'm still waiting to hear back from Altera on some of the issues I'm seeing, but overall, a working design is always better than a broken one :D
The TSE sources are actually in the Yocto patch, when I last looked. Either there or up on the Altera projects Github. But even reading examples takes time away from actual development!
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