Forum Discussion
Altera_Forum
Honored Contributor
9 years ago --- Quote Start --- OK, the *only* way to reset the IRQ line seems to be a reset to the mSGDMA core. That works, everything else fails. Is there anybody out there who can confirm that a s/w reset to the core is the only way the clear the IRQ line from the CSR slave? Note that I just use the write core without prefetcher or dispatcher. During packet video from CVI the kernel module monitors per completed transfer the amount of bytes sent and stops the dma core when a complete frame is transferred. The vsync of my sensor then triggers the start of a new frame. All works well now but I would really appreciate a less brutal way of clearing an interrupt request because that means I have to re-issue a descriptor after each interrupt. The FIFO structure and park-mode seem redundant now.... Arjan --- Quote End --- To get a grasp of this-- you're saying that writing a 1 to the status register doesn't work, and you need to trigger a s/w reset to the descriptor to clear any interrupts? I've never seen that-- I've been able to reset IRQ lines both with and without a prefetcher by writing to the status register. Now, if you're in park mode, this does get more complicated as the reset takes a finite amount of time, so you could be triggering an interrupt immediately after clearing it, creating a loop where the interrupt never seems to clear. I was wondering about the sender to the DMS, though-- is that packet-based, or in some way counting bytes being sent to the DMA separately from the kernel module? Without counting bytes in firmware, you're relying on the DMA alone. I found this leads to some odd behavior as the DMA has a FIFO associated with it that will fill asynchronously; meaning that if your firmware gets out of sync with your DMA operations, you could have stale data left in the buffer, and never be receiving your EOP, or always receving an EOP based on old data. I've found it much better to run in park mode and start and stop the module sending data to the DMA instead of the DMA itself as it better controls the data flow. What did they do in the SDI design example? I've only looked at the TSE design example, which also uses DMAs.