Honored Contributor
Honored ContributorOK, the *only* way to reset the IRQ line seems to be a reset to the mSGDMA core. That works, everything else fails.
Is there anybody out there who can confirm that a s/w reset to the core is the only way the clear the IRQ line from the CSR slave? Note that I just use the write core without prefetcher or dispatcher. During packet video from CVI the kernel module monitors per completed transfer the amount of bytes sent and stops the dma core when a complete frame is transferred. The vsync of my sensor then triggers the start of a new frame. All works well now but I would really appreciate a less brutal way of clearing an interrupt request because that means I have to re-issue a descriptor after each interrupt. The FIFO structure and park-mode seem redundant now.... Arjan
