--- Quote Start ---
Anyway, the question is: how do a clear the interrupt condition, or more likely, how do handle/clear events that lead to an interrupt?
--- Quote End ---
That's a fascinating issue. I had to build a valid signal controller that only sends the number of valids desired along with a clock-crossing FIF, and I still don't trust the module quite yet.
I'm just clearing interrupts from userspace right now, writing a 1 to the correct status register in the prefetcher, and that works fine for the speed that I'm running at. This really should be done in a simple kernel module, though, which is what I'd recommend. The Altera Workshops now up on rocketboard provide some great examples on that.
Now clearing events that led to an interrupt... I wonder if something is happening where the response port isn't lining up correctly with the EOP and other packet signals. I'm not using packets, but I wonder if someone else might have some idea about this.
Honored Contributor
