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What value is MAP_PIO_SIZE?
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Here's where things stand now:
- I can use them fine, but I am unable to cancel/reset an mSGDMA when using park mode. I think, to get around this, those mSGDMA modules will be started on startup and not touched after.
- Altera informed me that there was a synthesis bug that sometimes showed up related to descriptor writes in Quartus before 15.1.1, so I might have been seeing issues with that. Using the pre-fetcher works well for me, so I might try a no-prefetcher design again later.
- The mSGDMA module has a FIFO that it uses for the data path. This FIFO has a READY line out that ONLY signals that the FIFO is not full. This means that if doing an Avalon-ST to Avalon-MM DMA transaction the design must be very careful to NOT fill the FIFO while the DMA is not running, or you will see corrupted data. The fix for this is to have a module that only sends the number of valids that should go in to each DMA transaction each time.
Example: Start a single-shot of the DMA for n transactions, then start the FPGA-based streamer to send n transactions.
Example 2: Turn on DMA for park mode, then turn on transaction streamer. Stopping park should involve deasserting the bit, waiting for the Run to end, and then turning off the streamer before resetting the DMA. I have not been able to get this to work yet and instead the DMA gets stuck in reset.
It would be really nice if the DMA module "ready" was actually a "DMA ready to receive," but it is not.
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