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For any one else having issues, I was running in to an issue where the Qsys interconnect (or something on the Descriptor-write side) was causing problems with triggering the DMA, leading the DMA to act very odd.
Even so, I need to add a <100 ms delay after initiating and completing the first mSGDMA run before I can start using the DMA correctly. I'm wondering if there is some sort of initialization procedure that isn't covered by a reset that is not being accounted for?
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Has anyone been able to use the mSGDMA in park mode for an ST-to-MM transfer, and then reset the mSGDMA? I'm finding that I can't reset the DMA once I have started park mode, with the CSR getting stuck at a value of 0x5 (reset, run).
In addition, it looks like the mSGDMA only writes the Owned-by-HW bit during descriptor write back, meaning that having a linked list set up to point back at itself will fill the descriptor FIFO on the initial fetch. I might be wrong about this as well, but the documentation is very unclear.
BadOmen?
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