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And on a related note, how does the prefetcher handle fetching descriptors when the descriptor interface width is less than the full descriptor width? Does it fetch from LSB to MSB, or something else? If it fetches LSB to MSB, this will cause problems as the "GO" bit is in the MSB, which will then trigger a start without setting any of the interrupt enables.
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Up to the point now where the SDR ports are out of reset, and I am seeing data being streamed from the DMA in to RAM. The data ordering is odd, but I'm trying to do 128-bit transactions. I don't see why this would be an issue, but looking in to it.
EDIT: Spoke too soon. I'm able to get it to work once in awhile, but not consistently as expected. My procedure:
> Write updated descriptors in to descriptor memory
> Check for prefetcher to be stopped
> Trigger "run" and "global_int" bits of prefetcher
> Wait for run to end
> Wait for interrupt
It seems to sometimes work, sometimes not. Quite frustrating. The first run in a set seems to be missed, and unless I do things in a very specific way, no luck. It also seems to not be clearing the interrupt on the last run or clearing the interrupt takes longer than it should.
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