Forum Discussion
Altera_Forum
Honored Contributor
10 years agoI do control mSGDMA with lightweight AXI
In QSys: CSR, Descriptor, Response connected to lw_axi_master mm_write connected to f2h_axi_slave In Linux: open /dev/mem mmap to 0xFF200000 with offset of registers addresses
# pragma pack(push,1)
/**
* @brief mSGDMA control and status register
*/
typedef struct {
uint32_t status;
uint32_t control;
uint16_t rd_fill_level;
uint16_t wr_fill_level;
uint16_t resp_fill_level;
uint16_t reserved_0;
uint16_t rd_sequence_number;
uint16_t wr_sequence_number;
uint32_t reserved_1;
uint32_t reserved_2;
uint32_t reserved_3;
} t_mSGDMA_CSR;
# pragma pack(pop)
t_mSGDMA_CSR * regs_CSR;
fd_FPGA_ctrl_regs = open("/dev/mem", O_RDWR|O_SYNC);
mem_FPGA_ctrl_regs = (unsigned int*)mmap(NULL, MAP_PIO_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd_FPGA_ctrl_regs, 0xFF200000);
regs_CSR= (t_mSGDMA_CSR*)(p_mmap_mSGDMA_control + mSGDMA_CSR_offset / sizeof(uint32_t));
/* descriptor, response is the same */
/* and registers are ready to use */