mSGDMA and On-chip Memory

Even though this design is for Arria 10 SoC I would take a look at it to get a ballpark estimate of the performance you can expect from Cyclone V SoC: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html The design uses a baremetal program to control a bunch of mSGDMAs and pattern generator/checker cores in the FPGA to move data back and forth and measure the performance.

In the documentation subdirectory you'll find an excel spreadsheet with the numbers collected. The data shown is for the FPGA operating at 250MHz with 128-bit ports into the HPS and HPS SDRAM ports. In Cyclone V SoC if you have unidirectional data then what you could do is gang all the F2S ports together into a single 256-bit data path and move bulk data through it.