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Altera_Forum
Honored Contributor
Honored ContributorMounting usb flash stick
I am developing a USB IP core, and I am now at the stage where I am attempting to create a uClinux driver. With the new driver compiled into the kernel, and debug messages enabled, I see the f...
Altera_ForumHonored Contributor
Honored ContributorHello cetic,
<div class='quotetop'>QUOTE </div> --- Quote Start --- you say in the opencores project that the 50MHz oscillator on the Altera Nios evalboard must be changed by a 48MHz oscillator. I suppose this is because the USB ip in the FPGA must run at a specific frequency that cannot be generated by a PLL from the original 50MHz. Is this true ? If yes, what is that frequency ?[/b] --- Quote End --- The FPGA must run at 48MHz. If you only want to use low speed mode, then you can get away with using the PLL to generate 47.62MHz, but for full speed mode the USB 1.1 spec requires 0.05% clock tolerance.
