Minimal Cyclone V SE Testsystem on DE0-NANO-SOC: Uboot dies right after FPGA config

My QSys is as follows:

HPS Settings: (I only use the LW Bridge in 32 bit mode)

http://www.dbox2ide.de/html/Settings_Qsys.png

Peripheral Tab

http://www.dbox2ide.de/html/Settings_Qsys_peripherals.png

Input Clock Tab

http://www.dbox2ide.de/html/Settings_Qsys_clocks.png

Output Clock Tab

http://www.dbox2ide.de/html/Qsys_Clock_out.png

I've omitted the DDR settings. I assume the DDR Settings are correct as the LINUX runs stable.