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Honored ContributorMinimal Cyclone V SE Testsystem on DE0-NANO-SOC: Uboot dies right after FPGA config
Hi, I made a minimum System in Quartus 15.1. The Qsys Systems consist only of an AvalonMM UART and a 8 bit PIO for the LEDs. The only bridge used is the lightweight HPS4FPGA one (in32bit mode)....
Altera_ForumHonored Contributor
Honored ContributorMy QSys is as follows:
HPS Settings: (I only use the LW Bridge in 32 bit mode) http://www.dbox2ide.de/html/Settings_Qsys.png Peripheral Tab http://www.dbox2ide.de/html/Settings_Qsys_peripherals.png Input Clock Tab http://www.dbox2ide.de/html/Settings_Qsys_clocks.png Output Clock Tab http://www.dbox2ide.de/html/Qsys_Clock_out.png I've omitted the DDR settings. I assume the DDR Settings are correct as the LINUX runs stable.
