Methods of Halting/Stalling Nios II/f CPU, WAITREQUEST Scope and Access

Other than stopping the clock, is there a guaranteed way of halting or stalling the Nios II/f CPU without it losing its place (i.e., maintain PC, pipelines, and register values)?

I see the WAITREQUEST signals on both the instruction and data buses, but can those be asserted without the CPU actively accessing an associated Avalon MM interface? In other words, will the CPU stall if WAITREQUEST is asserted even if it is NOT actively accessing memory?

Here's my dilemma. I have tightly-coupled memories for both address and data. Both meet the requirements of 0 write latency, 1 cycle read latency, and usually no wait states. In other words, if the CPU isn't otherwise stalled, it will have full access.

However, I'd like to unconditionally stall or halt the CPU in its current location so that I can overlay memory updates.

I'm open to other recommendations or methods if you have them.

Also, do you know of a good, detailed description of the scope and timing of the WAITREQUEST signal Much of the Nios hardware reference seems to lack sufficient technical detail.