Occasional Contributor
Occasional Contributorhii frank thanks for your reply i saw in example design that is published in altera store called max10_rsu that they used both on chip flash and ram memory for the nios 2
i attached the picture of the nios 2 configurations and you can see that the picture that the nios 2 reset vector memory is configured to be generic quad spi controller and the exception vector memory is on chip memory
and if i understand you correctly i only need qspi as a memory for nios 2 ? so what do i need to do ? i built my system according to the altera example
1-do i need to set the exception vector also to generic quad spi controller also? and remove the on chip memory from my system
i be glad for help ?
Occasional ContributorHello
Can you check your design settings in Quartus with the example design settings, the link below provides the file for the example that you are trying to follow
Thanks
Occasional Contributorhii when i compile this project i get errors due to licince issues how can i solve it ?
Occasional ContributorHello
Let me check and get back to you. Thanks.
Occasional ContributorHello
Nios II is EOL, Altera stop selling Nios II/f license.
New users need to migrate to Nios V and apply the Nios V license.
Regarding the example design, couple of points below that can help you.
To simplify the design, it can be divided into three function blocks:
RSU block (Dual Configuration IP to handle RSU)
UART block (Communication thru UART, such as printf & scanf)
Booting block (Nios booting from QSPI)
Below User Guides will help you to understand more about these function blocks.
RSU block (Dual Configuration IP to handle RSU)
UART block (Communication thru UART)
Booting block (Nios booting from QSPI)
And finally connecting the 3 logic blocks to get the whole design,
Thanks
Occasional Contributorhii thanks a lot for reply that helped me alot
