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Altera_Forum
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14 years ago

master_waitrequest

Hi everybody, I have a problem in my nios II simulation. I have used the avalon memory-mapped master template for writting into a sdram memory. When I simulate the component and the master_writ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

That memory controller is not initialized/calibrated by Nios II, that is the old SDR SDRAM controller. Just like the newer DDR SDRAM controllers there is some time spend while the controller is coming up out of reset where it can't perform data accesses off-chip and as a result wait request must be asserted. I can't remember how long that delay is but 143us sounds about right.