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Altera_Forum
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14 years ago

master_waitrequest

Hi everybody, I have a problem in my nios II simulation. I have used the avalon memory-mapped master template for writting into a sdram memory. When I simulate the component and the master_writ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Is that the first/only cycle, part of a back to back sequence, or a single cycle separated by a lot of idle time?

It might be that the initialisation hasn't finished.

My experiments with SDAM seemed to imply that, under normal circumstances, the avalon cycle for isolated writes terminated immediately. My suspicions are that writes to adjacent addresses are buffered so that they can be sent as a burst.