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Altera_Forum's avatar
Altera_Forum
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14 years ago

master_waitrequest

Hi everybody, I have a problem in my nios II simulation. I have used the avalon memory-mapped master template for writting into a sdram memory. When I simulate the component and the master_writ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

OK I will try to answer myself, until 200000ns the sdram is not initialized by nios. After this time the waitrequest signal is reduced to 143ns.