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Altera_Forum
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12 years ago

Make file error in eclipse called from Quartus

1. Make file error 2. after programmed to board using verilog file, all lights are on no matter turn on or off switch, is it due to test bench module in top level file? will it affected c lan...
Altera_Forum's avatar
Altera_Forum
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9 years ago

How did you increase your RAM? I have the same problem using quartus 13.01.

I used SD ram in my qsys but I still have this problem while building the project in E-clipse.