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Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

What that error means is that you have to use Dedicated clock inputs that drive the PLL. FPGAs have Dedicated PLL inputs and dedicated PLL outputs which you need to use in order to maximize the data rate when using specific protocols such as LVDS. These Pins for the C10GX are :

PIN_N23/24

PIN_R23/24

PIN_U23/24

PIN_W23/24

Use these pins to feed the Ref Clk input to PLLs and this will solve the issue.

  • VRama10's avatar
    VRama10
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    In the Cyclone 10 GX board, I can see those 4 pins are used for SFP, PCIE, USB and FMC. In the example design that worked for 17.1, the PIN_AB16 was used as the refclk, but i's not working for 18.1

    PIN_N23/24 is dedicated for SFP,

    PIN_R23/24 is dedicated for PCIE,

    PIN_U23/24 is dedicated for USB,

    PIN_W23/24 is dedicated for FMC.

    I think in this case, either Intel has to change the layout of the board to let us use one of those four dedicated pins, or revert back the TSE IP core the way it was in 17.1