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SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
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6 years ago
Hello , Sorry.I am bit confused with your input . To make sure , are you using the same design for 17.1 and 18.1 ? from the Error it looks like PLL channel mapping issue. Do you getting this error during fitter right ? Would it possible to share the design if it is not confidential ? that make my life easy :) Thank you , regards, Sree
  • VRama10's avatar
    VRama10
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    6 years ago

    Hi,

    Yes, this error was during fitter in the compilation process. I'm using the same design as the one used for 17.1, in fact I loaded the design into 18.1 platform designer and just upgraded the IP, everything else remains the same.

    It's the Simple socket server example built for Cyclone 10 GX, I found somewhere in the Intel FPGA site.

    Please find the attached zip for the project that works with 17.1 and also the altered one from 17.1 to accommodate 18.1. I've added the files to the main query.

  • VRama10's avatar
    VRama10
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    6 years ago

    Please let me know if you any updates on this issue.