Low coremark benchmark score on Cyclone V (ARM Cortex A9)

Hi,

The problem is caused by a bug in the hwlib library. When building with armclang (-O2), some inline assembler functions are omitted which results in wrong cache/mmu configuration.

https://forums.intel.com/s/question/0D50P00004ABHFoSAP/missing-volatile-keyword-in-hwlib-inline-assembler-functions-armclang?language=en_US

As an example lets take a helper function from "alt_cache.c" file:

static __inline __attribute__((always_inline)) void sctlr_write_helper(uint32_t sctlr)

{

#if defined(__ARMCOMPILER_VERSION)

__asm("MCR p15, 0, %[sctlr], c1, c0, 0" : : [sctlr] "r" (sctlr));

#elif defined(__ARMCC_VERSION)

__asm("MCR p15, 0, sctlr, c1, c0, 0");

#else

__asm("MCR p15, 0, %0, c1, c0, 0" : : "r" (sctlr));

#endif

}

The armclang inline assembler requires the "volatile" keyword to be used like this:

static __inline __attribute__((always_inline)) void sctlr_write_helper(uint32_t sctlr)

{

#if defined(__ARMCOMPILER_VERSION)

__asm volatile ("MCR p15, 0, %[sctlr], c1, c0, 0" : : [sctlr] "r" (sctlr));

#elif defined(__ARMCC_VERSION)

__asm("MCR p15, 0, sctlr, c1, c0, 0");

#else

__asm("MCR p15, 0, %0, c1, c0, 0" : : "r" (sctlr));

#endif

}

Here is the link to the ARM documentation:

https://developer.arm.com/docs/100067/latest/armclang-inline-assembler/inline-assembly-statements-within-a-function/volatile