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alemannia
New Contributor
New ContributorLow coremark benchmark score on Cyclone V (ARM Cortex A9)
Hi, I'm using a low speed grade (-C8) Cyclone V with HPS (single core ARM Cortex A9). IC-5C SE B A4 U 19 C 8 S-TMP The code development is done on bare-metal (freeRTOS) with MPL as bootloader. All...
alemanniaNew Contributor
New ContributorA quick update on this issue.
When compiled with gcc or armcc, the coremark benchmark yields expected scores. It's the new arm clang compiler which gives the low score. Thus, our problem is not related to hardware or clock configuration.
