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Altera_Forum
Honored Contributor
7 years agoYes, it's the Cyclone 10GX development kit.
Yes, I have the J12 PCIe power connector connected to my PSU Yes, I tried both the enclosed master_image/top.sof file and re-built one using 17.1.0 Build 240. The resulting behavior is the same. This is what I tried:tar xvf ../Cyclone10GX_PCIeGen2x4_DMA_17_1_2.par
quartus_sh --restore 17.1.2/Cyclone10GX_PCIeGen2x4_DMA_17_1_2/Cyclone10GX_PCIeGen2x4_DMA_17_1_2.qar
find . -name '*.sof'|xargs md5sum
726940bdd434031299372ceeb1cae16e ./master_image/top.sof
After building using "Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition" I get the resulting sof file in output_files find . -name '*.sof'|xargs ls -l
-rw-r--r-- 1 petter petter 9061253 Mar 29 05:52 ./master_image/top.sof
-rw-r--r-- 1 petter petter 9061249 May 9 22:52 ./output_files/top.sof
Load the pre-built sof: quartus_pgm -c 'USB-BlasterII on zappa ' -m jtag -o p\;./master_image/top.sof@2
Boot the PCIe PC: pciebench~# reboot
PC will not boot. Can't even get into BIOS. Power cycle the PC (which will also wipe out the FPGA configuration loaded via JTAG) PC boots and I'm able to log in. Load the self-built sof: quartus_pgm -c 'USB-BlasterII on zappa ' -m jtag -o p\;./output_files/top.sof@2
pciebench ~# reboot
Same result. PC will not boot. I have no problems booting the PC if I load one of my test designs containing some simple logic to flash the LEDs and read data from the FPGA using JTAG. quartus_pgm -c 'USB-BlasterII on zappa ' -m jtag -o p\;/work/petter/fpga/builds/tests/cyclone-10gx-dev-kit/ce725c4+/project.sof@2
PC will boot fine, and I can log in. I will try to contact Altera to make sure I have the most recent example.