Forum Discussion
Altera_Forum
Honored Contributor
20 years ago --- Quote Start --- originally posted by paolo.gai@Dec 14 2005, 06:37 AM you did not say which software are you using on the device... is it the standard altera hal?
did you try to use non-blocking writes?
what do you use for the communication among the two cpus?
bye
paolo
<div align='right'><{post_snapback}> (index.php?act=findpost&pid=11536)
--- quote end ---
--- Quote End --- I am prototyping with the StratixII (DSP) evalboard, and stock drivers/libs are used. The data flow ( unidirectional for now ) : 2nd Nios2 -> UARTs -> UARTs -> Routing Nios2 -> JUARTs -> nios2-terminals There is no commuication between the NIOS2s All read/write by the "Routing Nios2" to the juarts/uarts are non-blocking. Read/write by the "2nd Nios2" are blocking calls.