Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

JTAG Hub, Avalon JTAG UART

Hi,

I'm looking for documentation about how to communicate with an Avalon JTAG UART from an external microcontroller. I have read ug_virtualjtag and thus know how i could implement communication using custom logic, but I really would like to access the generic JTAG UART. Why reinvent the wheel...

The first obstacle to overcome is the JTAG Hub. Is there any way to determine the number and type of virtual devices attached to the Hub? I can see in (traced) JTAG communication that IR sometimes is loaded with instructions longer than 10 bits (in a chain with only a single EP1C12F324), and instructions with code 0xC and 0xE appear quite often and seem to select a particular chain at the hub, maybe a register in the virtual device in that chain?

Second, I need to know how to communicate with the JTAG UART. It seems to me that there is a small IR in the JTAG Hub itself (3 or 5 bits?), which is polled until there is some data-available-bit set. Then the complete FIFO is read (10 bits per data byte?). But is it flushed at the same time? And how to write data to the FIFO(s) so that a Nios could receive it?

While I'm at it: it would also be convenient to know if there's a generic method to access any Avalon slave registers and memory contents (e.g. RAM) via JTAG...

Thanks for any hints

Kolja

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    --- Quote Start ---

    originally posted by kawk@Sep 3 2006, 02:03 AM

    instructions with code 0xc and 0xe appear quite often

    --- Quote End ---

    Ah, I think I understand how to access virtual JTAG devices: With 0xC or 0xE in the Cyclone's IR, during a following select/capture/shift/update DR cycle, the chain of virtual devices appears instead of the Cyclone in the real chain. Furthermore, with 0xE, the virtual devices select IR, not DR as in the real chain.

    This explanation may not be the full truth, but it is probably close. Are there any official names for these JTAG instructions 0xC and 0xE? The other questions from my original posting remain unanswered (yet)...

    Kolja
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    hi Kolja :

    how time flys,do you have hacked the jtag_uartt five years ago,

    today i am solvting the same question~

    Look forward to your reply:-P
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    FWIW I believe all the memory accesses are done by interrupting the nios cpu and getting it to action the request.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    FWIW I believe all the memory accesses are done by interrupting the nios cpu and getting it to action the request.

    --- Quote End ---

    ee~,:(i do not understand your meaning ~sorry for my poor english:oops:
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    What I meant was that the JTAG hardware interface isn't able to access any system memory.

    When the debugger requests a memory access, the JTAG hardware interrupts the nios cpu which performs the required memory access and send the response back to the debugger.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Many of the informations the original poster has been asking for is contained in the Virtual JTAG Megafunction User Guide 2.0 (Dec. 2008). Did you review it?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    If you have a SPI master on the external processor that connects to the FPGA you might find the design example called "SPI Slave to Avalon Master Bridge" to be a much easier way to do what you are attempting.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Many of the informations the original poster has been asking for is contained in the Virtual JTAG Megafunction User Guide 2.0 (Dec. 2008). Did you review it?

    --- Quote End ---

    thx for your reply,

    i think that isnot my needs, now i want to use miccontroller to communicate to the FPGA via its jtag_uart ,the fpga is running and cant hang up,so,i wanna kown how the jtag_uart transe data. and i found the the jtag instruct 'oxc,oxe' and send /recive data such as "1+flag+8bit(byte)" that the meaning is that use 10 bit to transe a byte. then i cant guass the init /handshake ;and "instructions with code 0xC and 0xE appear quite often"
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You need to work out what instructions 0xC and 0xE mean first, then it might be worth taking a look at the JTAG UART protocol which runs over some overlays of instruction 0xC. Be warned, it is quite complex.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    i think that isnot my needs

    --- Quote End ---

    Quite funny, that you are guessing about "instructions with code 0xC and 0xE". Reviewing the VirtualJTAG User guide about their exact meaning may be an alternative.