Issue using SGDMA to frame buffer

1) I would start with the embedded peripherals IP user guide because it documents the mSGDMA "macro" component. The documentation up on the wiki is for each core inside that macro component but you might find some details missing from the official document so you may want to cross reference between them.

2) There isn't any dependency between those two values. The maximum transfer length limits how big of a transfer can be performed with a single descriptor (useful when Fmax becomes a problem then you scale it back) and the data path FIFO depth is typically set to be larger than 4x the maximum burst size or deep enough to hide the read latency of the memory (you are writing to memory so that shouldn't matter).

3) Although packing the data improves the efficiency think about whatever is going to use this data after it's buffered in SDRAM. If it's going to be cumbersome for whatever consumes the data after to deal with packed data and you have enough memory bandwidth then I would just stuff every forth byte with zeros to keep each pixel aligned to 4 byte locations.

4) Ready in the write master is mainly hooked up to the internal fifo 'not full' signal. So when ready is high and you assert valid then the data is buffered into the write master and will eventually get written to memory. Packet support is only needed if you want to bound the transfer using start of packet and end of packet, since you already know what the video resolution is then you probably don't need that since you already know how much data is arriving per frame.