Honored Contributor
Honored ContributorThanks BadOmen for the speedy response. Some follow-up questions:
1. Where can I find the latest User Guide for the mSGDMA? I noticed a section dedicated in the Embedded Peripherals IP User Guide. But I also saw AlteraWiki page with a mSGDMA User Guide. 2. In mSGDMA Qsys GUI, is there any correlation between "Maximum Transfer Length" and the "Data Path FIFO Depth" settings? 3. In terms of my implementation, here is what I'm envisioning. My DDR3 has 128bit AV-MM interface in Qsys. So I'll set the mSGDMA with 128bit interface as well. I'll strip all the packet-related data from the AV-ST stream of the Clocked Video Input block. I'll pack multiple raw pixel values (24bit RGB ) into 128 bits, which will then be sent to the mSGDMA on the AV-ST port to be written to the DDR3 at a location defined by the descriptor. Am I on the right track here? 4. For the AV-ST interface on the mSGDMA, what does the 'READY' signal behaviour depend on? Is it dependent on whether the DATA FIFO is full or does it indicate when the data has been successfully written to the DDR3 memory? Also, for my application, should I enable Packet Support in the mSGDMA GUI? Thanks in advance!
