IORD_ALTERA_AVALON_PIO_DATA to slow?

Ok, the LPM-FIFO is no problem. If I connected my PIO to the ouput of the FIFO, I don't see how this could interface with a SGDMA. Because the SGDMA can read a whole block of memory (which is actually what I want), but the PIO only has a max. 32-Bit data register. I could just tell the SGDAM to read 4Bytes at a time using the API functions (mem-to-stream). The TSE has an internal transmit FIFO which is an Avalon-ST sink to the outside avalon bus. Would that be a solution? (LMP-FIFO -> PIO -> tx SGDMA -> TSE)

There is also an "On-Chip-FIFO" as an SOPC component and it could interface with the rx SGDMA. But I'd have trouble on the input side of that FIFO which is an Avalon-MM Slave. I would probably have to connect the PIO to there, but the PIO itself is only a MM-Slave.

Even another option could be that I write the ADC data into the DDR2 SDRAM. The DDR2 SDRAM-Controller looks pretty complex. I havn't figured out how I can write the ADC data on there. Because my SGDMA's are already connected to the RAM-Controller it would possible to read memory blocks from there.