IORD_ALTERA_AVALON_PIO_DATA to slow?

@Cris72: I've written a VHDL module (ad9254.vhd) that writes the data stream value on to the PIO port with every clock cycle of the ADC data clock (ada_dco). This clock has the same speed as the clock of the PIO component. (62,5MHz)

I've attatched the Top-Level Schematics of my System (tserd_3c120).

Hope that doesn't confuse.

@dsl: Yes, of course the sprintf() could take up time. I only use that to display the samples. Would it make a big enough difference if I wrote the samples into an array and then printed the content of that array? I'm still new to this whole Nios programming.

Would it be realistic to consider alternatives to the PIO such as a DMA or SGDMA? Or could it just be solved with a kind of a FIFO in hardware OR software?!