Interconnections and interrupts between nios processors

You would have to make a custom component containing a dual port memory. One side would be for Nios A and the other for Nios B. You map all the addresses from Nios A to the dual port memory straight through except for writing to one address. Writing to this address will cause an interrupt to Nios B. You need the same on the other side of the memory as well. This way you can write a message on the dual port memory and last write to the interrupt address and then the other Nios will know that there are a message to be picked up. For making QSYS components check out http://www.altera.com/literature/hb/qts/qsys_components.pdf