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Altera_Forum
Honored Contributor
Honored ContributorInterconnections and interrupts between nios processors
Hi, Now I am working on multi-core systms. Based on altera platform, more than two processors are using in a system and shard memory (message buffe) with Avalon-MM Pipeline Bridge is selected ...
Altera_ForumHonored Contributor
Honored ContributorTo Boris,
Thank you very much for your reply! Using SPI is not suitable for my case because communication between nios processors in our design needs high speed. I don't understand your second way exactly since I am a fresh to use Nios and Qsys. Would you like to tell me in details? Additionally, the interconnection between nios processors should be scalable, any suggestions?
