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Altera_Forum
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14 years ago

Interconnections and interrupts between nios processors

Hi, Now I am working on multi-core systms. Based on altera platform, more than two processors are using in a system and shard memory (message buffe) with Avalon-MM Pipeline Bridge is selected ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

You could use a multiple of ways. For example, SPI. Just have one SPI master on Nios A and a SPI slave on Nios B. This will come with interrupts etc so it should be easy to do. Then just have another set in the opposite direction.

You could also wrap the dual port memory in some code and generate interrupts for when you write to a certain address. This would give you the ability to tell the other processor when a message has been written. I have done this in the past and it works really well.

/Boris