Honored Contributor
Honored ContributorHi Nick,
> If this is actually supported It is. > a simple example will suffice. Here are a few: write a byte to i/o (bypass cache)#define readb(addr)
( { unsigned char val;
asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}
)#define CTL_STATUS 0 /* Processor status reg */# define CTL_ESTATUS 1 /* Exception status reg */# define CTL_BSTATUS 2 /* Break status reg */# define CTL_IENABLE 3 /* Interrut enable reg */# define CTL_IPENDING 4 /* Interrut pending reg */
# define _str_(x)# x
# define rdctl(reg)
( {unsigned int val;
asm volatile( "rdctl %0, ctl" _str_(reg) : "=r" (val) ); val;}
)
# define wrctl(reg,val)
asm volatile( "wrctl ctl" _str_(reg) ",%0": : "r" (val))
/* E.g.: foo = rdctl(CTL_IENABLE);
* wrctl(CTL_IENABLE, foo | 1);
*/
