Just as an update, I got my programs to download/verify and run again. I originally used the Altera provided calculations to phase shift the SDRAM clock, but I thought I should just try and recalculate everything. When I do this my calculations come out quite different than the Altera example where both of my lead numbers, for example, were negative. So I didn't know if I should take the lesser of the two? Take the absolute value of both and then negate one?
So, what I did was regenerate the system in SOPC, entirely recompile in Quartus, and then recalculate the SDRAM phase shift. I entered this, recompiled in Quartus, and now it seems to be working fine.
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