Honored Contributor
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<!--quotebegin-jdhar@Jun 7 2006, 09:32 AM in my mind, fpgas aren't as stable as lets say off-the-shelf processors. for example, there are problems on configuration sometimes from powerup, so you have to accunt for that in circuitry (crc checking). also, i have had problems with the avalon fabric itself locking up, so that has reduced my trust in fpgas. these are just a few of the issues. also, i haven't subjected them to temperature variations, so that's a big q-mark for me.
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--- Quote End --- Oh Ok. Regarding to temperature issues, I developped many FPGA design for my company, and each time we had to subject them to temperature variations (-30 °C/+70°C). And believe me, if your design is well coded (fully synchronous especially ), it works. Regarding to avalon fabric bug. What can be said ? ASIC are also prone to mask bug. With an ASIC , you have to wait for a new mask. With an FPGA you have to wait for a new design. So... By the way, what other issues do you talk about ? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=16001)</div> [/b] --- Quote End --- I'm glad to see that you have seen them proven in a wide temp. range. But just to be clear, I'm not making the argument that you should design your own ASIC over using an FPGA. FPGAs are great for quite a number of applications, and since I haven't done the necessary testing with the NIOS myself, I am just speculating at this point. However, getting an off the shelf processor that has been proven, with all of it's issues documented (if any), I think it would be safe to say that offers some security. I recognize that fixing bugs and documenting them all comes with time, and given the relative immaturity of NIOS 2, it's done quite well for it's lifespan. I just don't think it's at the point of maturity of lets say an Intel XScale. Take the lockup issue; I have been talking to altera reps for almost two months now, and not much has come out of it, even though they recognize the problem themselves. If a customer was to put out a design that used my specific setup which caused lockups, they would be in a lot of trouble since they had no prior knowledge of this, because it's not documented. Again, this will come with time... Please don't think I'm knocking FPGAs and NIOS. I have developed quite a few products around it myself (not as many as hippo!), so I obviously believe in it's potential. I'm just a bit hesitant in putting it with the same class as the other big-boys... maybe that hesitation is warranted, maybe not, I don't know. You asked about other issues I had... one in particular simply relates to the efficiency of such important cores as the DDR IP Core. If there are two cores that need to be working well together at all times, it shoudl be the NIOS and the memory core. I haven't found this to be true at all times. But of course, this is cured easily with upgrades... Hope this clarifies.
