implement DDR2/3 in SOPC

Those are Avalon-MM signals called burst count and burst begin. With that said if you go into the memory controllers in SOPC Builder you'll find that same memory controller with all the wiring done for you. You're master shouldn't provide burst begin, it is generated by the fabric. Your master should optionally provide the burst count though. If possible you could just widen the master data width and use the memory controller in halfrate mode. I'll just explain this with an example:

DDR2-SDRAM, x16 device (RAM burst length of 4 off-chip), 800MHz (effective)

Full rate mode slave port: x32, burst length of 2, 400MHz

Half rate mode slave port: x64, burst length of 1 (non-bursting), 200MHz

So half rate mode runs the slave port twice as wide and half the clock frequency and handles the off-chip burst of 4 internally so that your master doesn't need to worry about performing burst transactions. Both have the same offchip throughput and the only difference is the read latency is a bit higher in halfrate mode due to the clock crossing. Using 9.1 this clock crossing is very low latency and if you use an older version of the tools you can do this instead: http://www.nioswiki.com/exampledesigns/ddr_memory_half-rate_bridge