Forum Discussion
AnandRaj_S_Intel
Regular Contributor
7 years agoHi,
Have you implemented 4input NAND gate in entity nandg1?
y<= (a nand b) nand (c nand d);
should be like y<= (a nand b) or (c nand d);
Also check portmap L2.
Hi,
Have you implemented 4input NAND gate in entity nandg1?
y<= (a nand b) nand (c nand d);
should be like y<= (a nand b) or (c nand d);
Also check portmap L2.